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1 GRLIB IP Library User s Manual Version Jiri Gaisler, Sandi Habinc, Edvin Catovic Copyright Gaisler Research, 2008.Ģ 2 Table of contents 1 Introduction Overview Library organization On-chip bus Distributed address decoding Interrupt steering Plug&Play capability Portability Available IP cores Licensing LEON3 quick-start guide Introduction Overview Configuration Simulation Synthesis and place&route Simulation of post-synthesis netlist Board re-programming Running applications on target Flash PROM programming Installation Installation Directory organization Host platform support Linux Solaris Windows with Cygwin Windows with MingW CAD tool support - simulators Cadence NCsim GNU VHDL Simulator (GHDL) Modelsim VHDL and Verilog simulator Active-HDL VHDL and Verilog simulator Riviera VHDL and Verilog simulator Symphony-EDA Sonata VHDL simulator CAD tool support - synthesis Altera Quartus Cadence RTL Compiler (RC) Synplify FPGA Synopsys Design Compiler (DC) Xilinx XST Implementation flow Introduction Using Makefiles and generating scripts.